The present invention relates to a CMOS (complementary MOS) device wherein a p-channel MOS transistor and an n-channel MOS transistor are formed on the same semiconductor substrate and a method of manufacturing the same.
FIG. 6 is a sectional view showing the general structure of a p-well type of CMOS device. A used silicon (Si) semiconductor substrate 1 is an n-type, and a p-type well 2 is formed deep on the surface. An n-channel MOS transistor (hereinafter called N-MOS) 3 is formed on the surface of the p-type well 2. A p-channel MOS transistor (hereinafter called P-MOS) 4 is formed on the surface of the nxe2x88x92-type semiconductor substrate 1. n+-type regions 5A and 6A to be respectively a drain and a source of the N-MOS 3 are formed shallowly on the surface of the p-type well 2, and p+-type regions 7A and 8A to be respectively a drain and a source of the P-MOS 4 are formed shallowly on the surface of the semiconductor substrate 1. Further, a p-type channel stopper 9 is formed near the N-MOS 3 on the surface of the p-type well 2 and an n-type channel stopper 10 is formed near the P-MOS 4 on the surface of the semiconductor substrate 1 respectively to isolate the N-MOS 3 and the P-MOS4.
Element regions on the surface of the semiconductor substrate 1 having the internal structure described above are isolated by a thick field oxide film (SiO2) 11 and the field oxide film 11 is formed by local oxidation of silicon (LOCOS). A polycrystalline silicon layer 13 to be a gate electrode is formed on a gate oxide film 12 and hatched parts under the gate oxide film 12 respectively compose channel regions 1A and 2A. A boro-phosphosilicate glass (BPSG) film 14 for example is laminated on the surface of the whole device as an insulating film. Metallic wiring layers 15A, 15B and 15C made of aluminum (Al) are laminated on the BPSG film 14. The metallic wiring layers 15A, 15B and 15C are respectively connected to the source/drain regions 5A, 6A, 7A and 8A and the gate electrode 13 via a contact window open to a part of the BPSG film 14 and the oxide film thereunder.
However, in the CMOS device having the structure described above, withstand voltage between the drain and the channel was not enough. That is, there is a problem that in the N-MOS 3, the spread of a depletion layer on the side of n+-type drain 5A is small in operation, an electric field gradient between the drain region 5A and the pxe2x88x92-type channel region 2A becomes steep, the withstand voltage is decreased, also similarly in the P-MOS 4, an electric field gradient between the p+-type drain region 7A and the n-type channel region 1A becomes steep and the withstand voltage is decreased.
The invention is made in view of the situation described above and the object is to provide a CMOS device in which withstand voltage between its drain and its channel is increased.
Also, another object of the invention is to provide a CMOS device manufacturing method for readily forming the CMOS device.
In order to achieve the above object, according to the present invention, there is provided a CMOS device comprising:
a p-channel MOS transistor including a first p-type drain region provided with a first p-type impurity density;
a n-channel MOS transistor including a first n-type drain region provided with a first n-type impurity density,
a second p-type drain region formed in the first p-type drain region, and provided with a second p-type impurity density higher than the first p-type impurity density; and
a second n-type drain region formed in the first n-type drain region, and provided with a second n-type impurity density higher than the first n-type impurity density.
The CMOS device according to the invention is based upon a CMOS device having both a p-channel MOS transistor and an n-channel MOS transistor and is characterized in that the same conductive type of low density region is added to the drain region of the respective transistors to achieve the objects.
In this configuration, high impurity density regions are added to the respective drain regions, an electric field gradient between the drain region and the channel region under the operation of the device is made gentle and the withstand voltage is increased.
According to the present invention, there is also provided a method of manufacturing a CMOS device comprising the steps of:
preparing a semiconductor substrate having a first conductivity type;
forming a well region in the substrate, the well having a second conductivity type opposite to the first conductivity type;
implanting a first ion having the first conductivity type, into the well region to form a region to be a first drain region having a first impurity density and into the substrate to form a region to be a first channel stopper region;
implanting a second ion having the second conductivity type, into the well to form a region to be a second channel stopper region and into the substrate to form a region to be a the second drain region having a second impurity density;
thermally diffusing the respective ion implanted regions to form the first drain region and the second channel stopper region in the well region and to form the second drain region and the first channel stopper region in the substrate;
forming a third drain region in the first drain region so as to have the first conductivity type and a third impurity density higher than the first impurity density; and
forming a fourth drain region in the second drain region so as to have the second conductivity type and a fourth impurity density higher than the second impurity density.
In this configuration, to form the first and second drain regions, a new process is not required and the first and second drain regions can be formed in the same process for forming a channel stopper region.